Université Grenoble Alpes pushes chiplet security into the package itself

Researchers from Université Grenoble Alpes, CNRS and Grenoble INP have released a paper titled “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”, highlighted by Semiconductor Engineering. The issue is narrow but serious: the packaging architectures the chip industry is using to move beyond monolithic scaling also create new routes for side-channel attacks.

Chiplets are attractive because they let engineers assemble complex heterogeneous systems from several specialized pieces. Instead of one large monolithic die, a vendor can combine compute cores, memory blocks, accelerators and I/O logic through advanced 2.5D or 3D integration. That improves modularity, manufacturing yield and performance. The same physical closeness, shared infrastructure and dense interconnects also raise a harder question: what can one chiplet infer about another by observing the system’s side effects?

A side channel is not a conventional break-in through a password or exposed API. It is an attack that uses measurable traces of operation: power behavior, timing, electromagnetic effects or other physical and architectural signals. Those risks are already familiar in conventional chips. In advanced packaging, they acquire a new layout, because different chiplets sit close together, share parts of the operating environment and communicate at high speed.

That is why this research lands at the right moment. The industry is not moving to chiplets for academic neatness. It needs larger systems, more flexible design and better manufacturing economics. AI accelerators, server processors, communications chips and embedded platforms increasingly depend on heterogeneous integration. If the security model remains stuck at “each block was checked on its own,” the package becomes the place where vulnerabilities can hide between ownership boundaries, suppliers and IP cores.

The supply-chain angle is especially sensitive. Chiplet architecture encourages systems assembled from different sources. That is commercially useful, but it demands sharper security rules: who guarantees that one block cannot observe another, how isolation is verified, and what happens when components from different vendors meet inside the same 2.5D or 3D package?

The Grenoble work does not mean every chiplet system is suddenly unsafe. It means something more practical: security analysis has to move beyond the individual die and into the package itself. If chiplets are becoming the building format for advanced computing, then defense has to be designed at that level too, from physical layout and interconnects to testing, verification and contractual boundaries between partners. Otherwise the next generation of performance may arrive with a very old problem attached: data leaking through the behavior of hardware.